1. Field of the Invention
The present invention relates to a semiconductor memory integrated circuit (IC), and more particularly, to a semiconductor memory IC for a ball grid array package and a layout method of the same.
2. Description of the Related Art
In general, semiconductor manufactures produce semiconductor memory ICs and then package them into a variety of semiconductor packages. For example, many semiconductor memory ICs are packaged into a thin small outline package (TSOP) or in a ball grid array (BGA).
After being packaged, the characteristics of semiconductor memory ICs are tested. When a failure is detected in a semiconductor memory IC that is packaged in a TSOP or in a BGA package, characteristics of the semiconductor memory IC are changed by cutting a fuse. That is, a part of the package is opened to cut a fuse in a fuse circuit that is part of the semiconductor memory IC.
However, in the case of a semiconductor memory device packaged in a BGA package, the region to be opened is small in comparison to a semiconductor memory device packaged in a TSOP package. Therefore, in the case of a conventional semiconductor memory device packaged in a BGA package the fuse circuit is not exposed in the open region, and it is impossible to change characteristics of the semiconductor memory IC.
FIG. 1 is a plan view illustrating a conventional TSOP semiconductor memory device. The TSOP semiconductor memory device 100 includes pins 10 arranged on both sides of the package, and a semiconductor memory IC 200 having a plurality of cell array banks 20-1 to 20-4, peripheral circuits 22-1 and 22-2, and pads 24 arranged in the package.
The semiconductor memory IC 200 of FIG. 1 is arranged adjacent to one side of the pads 24. However, alternatively it can be arranged in a line adjacent to both sides of the pads 24.
FIG. 2 is a plan view illustrating a conventional BGA package semiconductor memory device. The BGA package semiconductor device 110 includes balls 12 arranged at a bottom of the package and a semiconductor memory IC 200 arranged in the package. The semiconductor memory IC 200 has the same configuration as that of FIG. 1.
The TSOP semiconductor memory IC 100 of FIG. 1 has a relatively wide open region which can be opened after the package test since the pads 10 are arranged at both sides. However, the BGA package semiconductor memory IC 110 of FIG. 2 has a relatively narrow region 16 which can be opened after the package test since the balls 12 are arranged at the bottom of the package.
FIG. 3 is a schematic view illustrating arrangement of the peripheral circuit in the semiconductor memory IC of FIGS. 1 and 2.
The peripheral circuits 22-1 and 22-2 are arranged as follows. Regions 30-1 to 30-3 on which circuits are arranged are sequentially arranged in a transverse direction at locations adjacent to the pads 24. Metal lines 32-1 to 32-6 which apply a power voltage to upper portions of the regions 30-1 to 30-3 are sequentially arranged in a transverse direction. Signal lines 34-1 to 34-3 are sequentially arranged in a transverse direction between the regions 30-1 to 30-3.
Control circuits 40-1 to 40-3 are respectively arranged on corresponding portions of the regions 30-1 to 30-3. Fuse circuits 42-1 to 42-3 are respectively arranged between the respective signal lines 34-1 to 34-3. The respective control circuits 40-1 to 40-3 and the respective signal lines 34-1 to 34-3 are arranged adjacent to each other.
The fuse circuits 42-1 to 42-3 generate control signals CON1 to CON3, respectively, when their fuses are cut off. The control circuits 40-1 to 40-3 generate output signals OUT1 to OUT3 by delaying or not delaying input signals IN1 to IN3 in response to the control signals CON1 to CON3, respectively.
Therefore, when the semiconductor memory IC having an arrangement of the peripheral circuit as shown in FIG. 3 are packaged into the TSOP or the BGA package, the TSOP package semiconductor memory device of FIG. 1 can change characteristics after the package test because all of the fuse circuits 42-1 to 42-3 of each of the peripheral circuits 22-1 to 22-3 can be opened, whereas in the BGA package it is impossible to change characteristics by the fuse circuits 42-1 and 42-2 after the package test because all of the fuse circuits 42-1 to 42-3 of each of the peripheral circuits 22-1 to 22-3 can not be opened. Changing the characteristics of the semiconductor memory IC is similar to lowering or raising a voltage level or to delaying or advancing an enable time point of a sense amplifier enable control signal.
Also, a conventional semiconductor memory IC has a relative large layout area size because the fuse circuits 42-1 to 42-3 are arranged between the regions 30-1 to 30-3 and so the signal lines 34-1 to 34-3 can not be arranged over the fuse circuits 42-1 to 42-3.
When a conventional semiconductor memory IC is packaged into the BGA package, there is a problem in that its characteristics can not be changed because the fuse circuits are not exposed after the package test.
The conventional semiconductor memory IC further has a problem in that a layout area size is increased because the fuse circuits are arranged between the regions on which circuits are to be arranged.